1. Field of the Invention
The present invention relates generally to semiconductor memory devices and manufacturing methods thereof and, more particularly, to a dynamic random access memory (hereinafter referred to as DRAM) including a capacitor having stacked structure, a so-called stacked capacitor cell and a method of manufacturing such a DRAM.
2. Description of the Background Art
In recent years, with wider propagation of information apparatus such as computers, semiconductor memory devices have been rapidly in great demand. Further, highly reliable semiconductor memory devices having large memory capacities with respect to function are required. Under such circumstances, technology for fabrication of highly integrated and highly reliable semiconductor memory devices has been developed.
A DRAM is one of the semiconductor memory devices, which enables random input and output of storage information. The DRAM includes in general a memory cell array having a storage region for storing a large amount of storage information and peripheral circuits required for external inputs and outputs.
FIG. 5 is a block diagram showing a general structure of the DRAM. Referring to FIG. 5, a DRAM 50 includes a memory cell array 51, a row and column address buffer 52, a row decoder 53, a column decoder 54, a sense refresh amplifier 55, a data-in buffer 56, a data-out buffer 57 and a clock generator 58. Memory cell array 51 serves to store a data signal as storage information. Row and column address buffer 52 serves to externally receive address signals A.sub.0 -A.sub.9 for selecting a memory cell constituting a unitary storage circuit. Row decoder 53 and column decoder 54 serve to decode the address signals to designate a memory cell. Sense refresh amplifier 55 serves to amplify signals stored in the designated memory cell and to read the amplified signals. Data-in buffer 56 and data-out buffer 57 serve to input and output data. Clock generator 58 generates a clock signal to control for each portion.
Memory cell array 51, occupying a large area on a semiconductor chip, is formed of a plurality of arranged memory cells for storing unitary storage information. FIG. 6 is a diagram showing an equivalent circuit of the memory cells of 4 bits constituting memory cell array 51. Memory cell array 51 includes a plurality of word lines 1a, 1b, 1c and 1d extending in parallel in the direction of rows and a plurality of bit lines 2a and 2b extending in parallel in the direction of columns. Memory cells 3 are formed near the intersections between word lines 1a-1d and bit lines 2a and 2b. Each of memory cells 3 includes one MOS (Metal Oxide Semiconductor) transistor 4 and one capacitor 5. Such a configuration as shown in FIG. 6 that a pair of bit lines 2a and 2b are arranged in parallel to sense refresh amplifier 55 is called a folded bit line system.
A planar arrangement of the DRAM shown in the equivalent circuit diagram of FIG. 6 is shown in FIG. 7. FIG. 7 shows four memory cells including respective sets of MOS transistors Q1, Q2, Q3 and Q4 and capacitors Cs1, Cs2, Cs3 and Cs4 formed in respective operation regions A1, A2, A3 and A4. Gate electrodes constituting transistors Q1-Q4 are formed of portions of word lines 1a-1d corresponding to the respective memory cells. Bit lines 2a and 2b are formed to be insulated from and crossing at right angles to word lines 1a-1d above the word lines. Bit lines 2a and 2b are connected to the memory cells through contact holes C1, C2 and C3.
Next, a cross sectional structure of the memory cells taken along the line VIII--VIII of FIG. 7 is shown in FIG. 8. FIG. 8 shows memory cells 3 of 2 bits. Memory cell 3 includes one MOS transistor 4 and a capacitor 5. MOS transistor 4 includes a pair of source/drain regions 6a and 6b formed to be spaced apart from each other in a surface of a silicon substrate 40, and gate electrodes 8 (1b, 1c) formed on the surface of silicon substrate 40 with a gate oxide film 7 sandwiched therebetween. Capacitor 5 includes a lower electrode (a storage node) 9 connected to one of the source/drain regions 6a of MOS transistor 4, a dielectric layer 10 formed on an upper surface of lower electrode 9, and an upper electrode (a cell plate) 11 covering an upper surface of dielectric layer 10. Lower electrode 9 and upper electrode 11 are formed such as of polysilicon. The capacitor having the above-described stacked structure is called a stacked capacitor. Stacked capacitor 5 has a portion thereof extending over gate electrodes 8 with an insulator film 12 sandwiched therebetween and the other portions thereof extending over a field oxide film 13. A thick interlayer insulation film 14 covers the surface of silicon substrate 40 where capacitor 5 and the like are formed. Bit line 2b formed on interlayer insulation film 14 is connected to the other source/drain region 6b of MOS transistor 4 through a contact hole 15.
In general, the capacitance of capacitor 3 is proportional to a counter area between lower electrode 9 and upper electrode 11 opposing to each other with dielectric layer 10 therebetween. Thus, this counter area should be increased in order to increase the capacitance of capacitor 3. However, the elementary structure of a DRAM has become more miniaturized. A method in which a planar occupied area is reduced for higher integration has been adopted as to memory cell structure. Accordingly, the planar occupied area of a capacitor has been limited and reduced. A decrease in counter area between the electrodes of capacitor 5 causes a decrease in capacitance of the capacitor, resulting in the following problems.
(i) When the capacitance of capacitor 5 decreases, the magnitude of read signals from capacitor 5 decreases. Accordingly, the sensitivity of a storage signal decreases, and the reliability of the DRAM also decreases.
(ii) Erroneous operations are liable to occur due to occurrence of soft errors caused by .alpha.-ray.
As described above, the decrease in capacitance of the capacitor causes a degradation in essential function of the DRAM, leading to significant problems.
To eliminate the foregoing disadvantages, a DRAM having such capacitor structure that the reduction in planer occupied area of the capacitor does not cause the decrease in capacitance of the capacitor is proposed. FIG. 9 is a partial cross sectional view showing the structure of a stacked capacitor proposed in, e.g., IEDM (International Electron Devices Meeting) 88, pp. 596-599. In this structure, a capacitor is formed on a bit line. Referring to FIG. 9, gate electrodes 101b and 101c serving also as word lines are formed to be spaced apart from each other on a silicon substrate 140 with a gate oxide film 107 sandwiched therebetween. Source/drain regions 106a and 106b spaced apart from each other by gate electrode 101c are formed in silicon substrate 140. A bit line 102b is formed to be connected with source/drain region 106b. Bit line 102b is formed above word lines 101b and 101c with an insulator film 112 therebetween. A storage node 109 is formed on bit line 102b with an insulator film 114 therebetween. Storage node 109 is formed to electrically come into contact with source/drain region 106a. A cell plate 111 is formed to oppose to storage node 109 with a dielectric film 110 sandwiched therebetween. In this manner, bit line 102b is formed in the lower layer of storage node 109 as a capacitor and cell plate 111. This enables storage node 109 and cell plate 111 to be formed so that bit line 102b may extend over a contact portion connected to source/drain region 106b. This makes it possible to increase the counter area between the two electrodes constituting the capacitor and thus to increase the capacitance of the capacitor.
Such structure that the capacitance of the capacitor is further increased in the stacked capacitor shown in FIG. 9 has been proposed. FIG. 10 is a partial cross sectional view showing the structure of a stacked capacitor proposed in IEDM 88, pp. 592-595. Referring to FIG. 10, gate electrodes 201b and 201c serving also as word lines are formed to be spaced apart from each other on a silicon substrate 240 with a gate oxide film 207 sandwiched therebetween. Source/drain regions 206a and 206b spaced apart from each other by gate electrode 201c are formed in silicon substrate 240. A bit line 202b is formed to be connected with source/drain region 206b. An insulator film 212 is formed between bit line 202b and word lines 201b and 201c. A storage node 209 is formed on bit line 202b with an insulator film 214 sandwiched therebetween. This storage node 209 has a so-called fin structure in which a lower portion thereof is formed to electrically come into contact with source/drain region 206a, and an upper portion thereof is branched to require a larger surface area. A dielectric film 210 is formed to cover the surface of the branched fins of storage node 209. A cell plate 211 is formed to oppose to the surface of the branched fins of storage node 209 with dielectric film 209 interposed therebetween. Branching the upper portion of storage node 209 and then surrounding the surface of the branched fins of storage node 209 by cell plate 211 as described above causes an increase in counter area between the two electrodes constituting a capacitor, thereby to increase the capacitance of the capacitor.
In this capacitor structure, however, the upper portion of the storage node is required to be forked into a number of branches. It is thus anticipated that the manufacture of the branched storage node causes a complication in the manufacture process, leading to a significant degradation of production yield with respect to mass production. Moreover, according to this structure, the cell plate of a top layer can be formed to extend to bottom portions of the storage node formed in electrical contact with the source/drain region; however, it is difficult to form the cell plate located beneath the storage node so as to extend to the roots of the storage node.